Implementing simultaneous read and write operations utilizing dual port dram

ABSTRACT

A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field,and more particularly, relates to a method, system and memory controllerfor implementing simultaneous read and write operations in a memorysubsystem utilizing a dual port Dynamic Random Access Memory (DRAM)configuration.

DESCRIPTION OF THE RELATED ART

Today's workloads can be very dynamic and as such memory subsystemsshould be designed with a certain degree of adaptability.

A need exists for an effective mechanism to enable enhanced memorysubsystem adaptability and enhanced performance under certainconditions.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method,system and memory controller for implementing simultaneous read andwrite operations in a memory subsystem utilizing a dual port DynamicRandom Access Memory (DRAM) configuration. Other important aspects ofthe present invention are to provide such method, system and memorycontroller and DRAM configuration which can, under certain conditions,double the number of accesses, substantially without negative effectsand that overcome some of the disadvantages of prior art arrangements.

In brief, a method, system and memory controller are provided forimplementing simultaneous read and write operations in a memorysubsystem utilizing a dual port Dynamic Random Access Memory (DRAM)configuration. A DRAM includes a first partition and a second partition.A memory controller determines if memory requirements are above or belowa usage threshold. If the memory requirements are below the usagethreshold, the memory is partitioned into a read buffer and a writebuffer, with writes going to the write buffer and reads coming from theread buffer, data being transferred from the write buffer to the readbuffer through an Error Correction Code (ECC) engine. If the memoryrequirements are above the usage threshold, the entire memory is usedfor reads and writes.

In accordance with features of the invention, the memory controllersends the DRAM at least one mode register set (MRS) command to setup thedual port DRAM configuration with the memory partitioned into a readbuffer and a write buffer.

In accordance with features of the invention, the write buffer receivesdata including ECC from the bus, this data is held until an internalECC, Reliability, Availability, and Serviceability (RAS), control logicof the DRAM is able to validate and transfer the data to the readbuffer. Once data is transferred into the read buffer, it will beavailable for read operations, effectively allowing the system toperform reads and writes simultaneously.

In accordance with features of the invention, if the memory requirementsare above the usage threshold, the memory controller will temporarilystop data flow and commands into that DRAM. This is the first step inthe transition from the dual port configuration to a single portconfiguration. The memory controller must guarantee that sufficient timeelapses so that the internal ECC, RAS, control logic of the DRAM is ableto transfer all incoming data into the read buffer. This will ensurethat all the data in the read buffer is exactly the same as the data inthe write buffer. Finally, an MRS command is sent to disable dual portconfiguration.

In accordance with features of the invention, once the buffers aremirror copies of each other the memory controller can re-assign thelowest order address bits to the first location of the read buffer. Thiswill ensure that the data is valid and ready for use prior to releasingthe DRAM for single port operation. The final step will require an MRScommand that will clear all the data on the write buffer, returning theDRAM to its normal capacity.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention together with the above and other objects andadvantages may best be understood from the following detaileddescription of the preferred embodiments of the invention illustrated inthe drawings, wherein:

FIG. 1 illustrates an example computer system for implementingsimultaneous read and write operations in a memory subsystem utilizing adual port Dynamic Random Access Memory (DRAM) configuration inaccordance with preferred embodiments;

FIG. 2 illustrates exemplary functions of the memory subsystem of FIG. 1for implementing simultaneous read and write operations in accordancewith preferred embodiments;

FIG. 3 is a flow chart illustrating exemplary operations forimplementing simultaneous read and write operations in the memorysubsystem of FIG. 1 in accordance with preferred embodiments;

FIG. 4 is a block diagram illustrating a computer program product inaccordance with the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of embodiments of the invention,reference is made to the accompanying drawings, which illustrate exampleembodiments by which the invention may be practiced. It is to beunderstood that other embodiments may be utilized and structural changesmay be made without departing from the scope of the invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

In accordance with features of the invention, a method, system andmemory controller are provided for implementing simultaneous read andwrite operations in a memory subsystem utilizing a dual port DynamicRandom Access Memory (DRAM) configuration.

Having reference now to the drawings, in FIG. 1, there is shown anexample computer system generally designated by the reference character100 for implementing simultaneous read and write operations in a memorysubsystem utilizing a dual port Dynamic Random Access Memory (DRAM)configuration in accordance with the preferred embodiment. Computersystem 100 includes one or more processors 102 or general-purposeprogrammable central processing units (CPUs) 102, #1-N. As shown,computer system 100 includes multiple processors 102 typical of arelatively large system; however, system 100 can include a single CPU102. Computer system 100 includes a cache memory 104 connected to eachprocessor 102.

Computer system 100 includes a memory system 106 including a memorycontroller 108 and a main memory 110 connected by a bus 112. Bus 112 isone or more busses that send address/command information to main memory110 and send and receive data from the memory 110. Main memory 110 is arandom-access semiconductor memory for storing data, including programs.Main memory 110 is comprised of, for example, a dynamic random accessmemory (DRAM), a synchronous direct random access memory (SDRAM), acurrent double data rate (DDRx) SDRAM, non-volatile memory, opticalstorage, and other storage devices.

I/O bus interface 114, and buses 116, 118 provide communication pathsamong the various system components. Bus 116 is a processor/memory bus,often referred to as front-side bus, providing a data communication pathfor transferring data among CPUs 102 and caches 104, memory controller108 and I/O bus interface unit 114. I/O bus interface 114 is furthercoupled to system I/O bus 118 for transferring data to and from variousI/O units.

As shown, computer system 100 includes a storage interface 120 coupledto storage devices, such as, a direct access storage device (DASD) 122,and a CD-ROM 124. Computer system 100 includes a terminal interface 126coupled to a plurality of terminals 128, #1-M, a network interface 130coupled to a network 132, such as the Internet, local area or othernetworks, and a I/O device interface 134 coupled to I/O devices, such asa first printer/fax 136A, and a second printer 136B.

I/O bus interface 114 communicates with multiple I/O interface units120, 126, 130, 134, which are also known as I/O processors (IOPs) or I/Oadapters (IOAs), through system I/O bus 116. System I/O bus 116 is, forexample, an industry standard PCI bus, or other appropriate bustechnology.

Computer system 100 is shown in simplified form sufficient forunderstanding the present invention. The illustrated computer system 100is not intended to imply architectural or functional limitations.Although main memory 110 of main memory system 106 is representedconceptually in FIG. 1 as a single entity, it will be understood that infact the main memory is more complex. In particular, main memory system106 comprises multiple modules and components. The present invention canbe used with various hardware implementations and systems and variousother internal hardware devices.

An example memory subsystem, for example, of the main memory system 106is illustrated and described with respect to FIG. 2 for implementingsimultaneous read and write operations in a memory subsystem utilizing adual port Dynamic Random Access Memory (DRAM) configuration.

Referring to FIG. 2, there is shown a high level block diagramillustrating example memory subsystem generally designated by thereference character 200 in the memory system 106 in accordance with thepreferred embodiments.

In accordance with features of the invention, the memory subsystem 200with the Dynamic Random Access Memory (DRAM) separated into two equalbuffers, a read buffer 202 and a write buffer 204 in the dual portDynamic Random Access Memory (DRAM) configuration. The write buffer 204receives incoming data from a system bus 208, while the read buffer 202provides ECC verified data back to the bus 208. An internal ECC,Reliability, Availability, and Serviceability (RAS), control logic 206of the DRAM is able to validate and transfer the data to the read buffer202. The memory subsystem 200 includes a memory controller 210 and anError Correction Code (ECC) generation function 212 or ECC engine.

In accordance with features of the invention, the memory subsystem 200includes the ECC, RAS, control logic 206 for use in the dual port DRAMconfiguration. The memory subsystem 200 performs scrub to the writememory buffer 204 only during dual port configuration, with an entryinvalidated and marked unusable if an error occurs during the scrubbingprocess. Data is ECC checked as it is transferred from the write buffer204 to the read buffer 202.

In accordance with features of the invention, the read and writeoperations are performed simultaneously, greatly increasing theperformance of the memory subsystem 200 in the dual port DRAMconfiguration. For example, the memory performance can be increased by afactor of two while the memory subsystem 200 in the dual port DRAMconfiguration. The memory controller 212 determines if current workloaddemands additional resources beyond a specified threshold the memoryspace would then be configured in a single port configuration on the flyto maximize capacity rather than performance.

Referring to FIG. 3, there are shown exemplary operations forimplementing simultaneous read and write operations in the memorysubsystem 200 utilizing a dual port Dynamic Random Access Memory (DRAM)configuration in accordance with one preferred embodiment starting at ablock 300. As indicated in a block 302, system power on begins. Asindicated in a decision block 304, the memory controller 210 determinesif memory requirements are above or below a usage threshold, forexample, if the workload is less than 50% of memory space. If the memoryrequirements are below the usage threshold, the memory controller sendsthe DRAM at least one mode register set (MRS) command to setup the dualport DRAM configuration with the memory partitioned into a read bufferand a write buffer as indicated in a block 306. As indicated in a block308, the memory controller 210 temporarily stops data flow and commandsinto the DRAM data bus. The memory subsystem is partitioned to create aread buffer and a write buffer as indicated in a block 310. The memorysubsystem is set to the dual-port mode with writes going to the writebuffer and reads coming from the read buffer, data being transferredfrom the write buffer to the read buffer through an Error CorrectionCode (ECC) RAS control logic as indicated in a block 312. Thenmonitoring the workload continues at decision block 304.

If the memory requirements are above the usage threshold, the entirememory is used for reads and writes with the DRAM configured in a singleport DRAM configuration. As indicated in a block 314, the memorycontroller 210 temporarily stops data flow and commands into the DRAMresponsive to the memory requirements being above the usage threshold.As indicated in a block 316, the memory controller must guarantee thatsufficient time elapses providing a buffer command delay so that theinternal ECC, RAS, control logic of the DRAM is able to transfer allincoming data into the read buffer. The memory controller sends the DRAMat least one mode register set (MRS) command to disable the dual portDRAM configuration as indicated in a block 318. As indicated in a block320, once the buffers are minor copies of each other the memorycontroller can re-assign the lowest order address bits to the firstlocation of the read buffer. This will ensure that the data is valid andready for use prior to releasing the DRAM for single port operation. Thefinal step will require an MRS command that will clear all the data onthe write buffer as indicated in a block 322, and the memory subsystemis set to the single port mode returning the DRAM to its normal capacityas indicated in a block 324. Operations end as indicated in a block 326.

Referring now to FIG. 4, an article of manufacture or a computer programproduct 400 of the invention is illustrated. The computer programproduct 400 is tangibly embodied on a non-transitory computer readablestorage medium that includes a recording medium 402, such as, a floppydisk, a high capacity read only memory in the form of an optically readcompact disk or CD-ROM, a tape, or another similar computer programproduct. Recording medium 402 stores program means 404, 406, 408, and410 on the medium 402 for carrying out the methods for implementingsimultaneous read and write operations in a memory subsystem 200utilizing a dual port Dynamic Random Access Memory (DRAM) configurationof FIG. 2.

A sequence of program instructions or a logical assembly of one or moreinterrelated modules defined by the recorded program means 404, 406,408, and 410, direct the memory subsystem 200 for implementingsimultaneous read and write operations in a memory subsystem 200utilizing the dual port Dynamic Random Access Memory (DRAM)configuration of the preferred embodiments.

While the present invention has been described with reference to thedetails of the embodiments of the invention shown in the drawing, thesedetails are not intended to limit the scope of the invention as claimedin the appended claims.

1-9. (canceled)
 10. A memory system for implementing simultaneous readand write operations in a memory subsystem utilizing a dual port DynamicRandom Access Memory (DRAM) configuration comprising: a DRAM includes afirst partition and a second partition; a memory controller, said memorycontroller determining if memory requirements are above or below a usagethreshold; said memory controller responsive to the memory requirementsbeing below the usage threshold, partitioning the DRAM into a readbuffer and a write buffer, with writes going to the write buffer andreads coming from the read buffer, data being transferred from the writebuffer to the read buffer through an Error Correction Code (ECC) engine;and said memory controller responsive to the memory requirements beingabove the usage threshold, using the entire DRAM for reads and writes.11. The memory system as recited in claim 10, includes control codestored on a computer readable medium, and wherein said memory controlleruses said control code to implement simultaneous read and writeoperation.
 12. The memory system as recited in claim 10 includes saidmemory controller initially sending at least one mode register set (MRS)command to setup the dual port DRAM configuration with the DRAMpartitioned into the read buffer and the write buffer.
 13. The system asrecited in claim 12 includes said memory controller transferring data tothe write buffer including ECC from the bus, the data being held untilan internal ECC, Reliability, Availability, and Serviceability (RAS),control logic of the DRAM is able to validate and transfer the data tothe read buffer.
 14. The system as recited in claim 13 includes saidmemory controller effectively allowing the system to perform reads andwrites simultaneously responsive to the data being transferred into theread buffer.
 15. The system as recited in claim 10 includes said memorycontroller responsive to the memory requirements being above the usagethreshold, temporarily stop data flow and commands into the DRAM totransition from the dual port configuration to a single portconfiguration.
 16. The system as recited in claim 15 includes saidmemory controller providing a buffer command delay.
 17. The system asrecited in claim 15 includes said memory controller sending at least onemode register set (MRS) command to disable the dual port DRAMconfiguration
 18. The system as recited in claim 15 includes said memorycontroller providing data in the read buffer as mirror copy of data inthe write buffer.
 19. The system as recited in claim 18 includes saidmemory controller providing data in the read buffer as mirror copy ofdata in the write buffer.
 20. The system as recited in claim 19 includessaid memory controller providing the DRAM set to a single portconfiguration mode.